Implement a NAND gate using only four CMOS transistors. Draw the CMOS NAND gate to aid in writing the Verilog code. The automatic testing does not ensure that only transistors were used. The submission will be manually reviewed to check if only transistors were used.Exercise 2 [2.0]LOCKEditor module nandgate(output logic y, input logic a, b; supply vdd; supply gnd; wire gateout;Test BenchSimulation OutputRun// Using only PMOS, NMOS, and wires, implement a NAND gateassign y = gateout;endmodule
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Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance between the output node and ground. Compare the values of tP L H and tP H L, obtained when the devices are sized as in Fig. 13.36, to the values obtained when all n -channel devices have W / L=n and all p -channel devices have W / L=p.
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