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2. The drawn mask layout of a CMOS logic gate is shown below. Assume a p-type silicon substrate.VDDGNDVAVBVoutmetalpolysilicon(a). Draw the schematic diagram of the CMOS transistor circuit using standard circuit symbols.Make sure that all the terminals of the transistors and the circuits are clearly labeled.(b). Using the scalable CMOS layout design rules or also called λ layout design rules, determinethe transistor size (i.e. W/L) of each transistor of the logic circuit.
2. The drawn mask layout of a CMOS logic gate is shown below. …
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