Industry Articles Improving ASIC Design Verification using FPGAs and Structured ASICs - April 10, 2007 Pat Mead, Altera Europe High Wycombe, UK Abstract : Structured ASICs require developers to ...

An important aspect of this type of ASIC platform involves the way the various metal layers are used. In a process that has five metal layers, for example, the bottom three layers may be used to ...

Today, few tools support formal verification in FPGA designs. In the ASIC world, formal verification and equivalency checking are well-known error-checking techniques.

As the IC/ASIC industry matures, as expected, we’ve seen a trend of verification technology adoption peaking (that is, leveling off), as shown in Figure 13. Figure 13. IC/ASIC Dynamic Verification ...

Designers think of platform array technology as a way to save fabrication time, but this type of ASIC is equally effective at saving design time — including DFT — and verification time. The design ...