However, I will point out a few key areas that trip up new FPGA designers and by following the example code, you’ll be up to speed in no time. For part I, you need a Verilog simulator.

Bringing C language synthesis to FPGA design, Aldec on Wednesday (May 21) rolled out its Active-HDL version 6.1 toolset offering an interface to Celoxica's DK2 Design Suite. The interface lets FPGA ...