Semiconductor Engineering

Wafer Test Challenges For Chiplets

In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage.
EDN

Inspecting the wafer test

Wafer inspection has become a critical part of the semiconductor manufacturing process. Inspections performed after wafer test can analyze the marks left by probe cards to ensure that the test process ...
Electronic Design

Test strategy implications on cost of test

Test strategy analysis has become increasingly important for finding ways to reduce test costs for system-on-a-chip (SoC) semiconductor devices. Every SoC device’s test flow is unique and requires a ...
Electronic Design

Wafer-Level High-Power Device Testing

Keeping an IC cool takes on new meaning when power dissipation exceeds 150 watts. Innovative electrical and mechanical solutions to new wafer testing challenges continue to be developed. For example, ...
Nasdaq

Aehr to Showcase FOX-P™ Wafer-Level, Die and Module Test Solutions at Virtual SWTest Untethered 2020 Conference on November 11

FREMONT, Calif., Nov. 09, 2020 (GLOBE NEWSWIRE) -- Aehr Test Systems (NASDAQ: AEHR), a worldwide supplier of semiconductor test and reliability qualification equipment, will be showcasing its FOX-P™ ...
Nasdaq

Aehr Receives Order from New Customer for FOX-NP(TM) Multi-Wafer Test and Burn-in System for Silicon Carbide Power MOSFETs

FREMONT, CA / ACCESSWIRE / April 2, 2024 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial customer order ...