EDN

Aldec Brings Mixed VHDL/Verilog/SystemC Verification to Mainstream Designers

Aldec, Inc., announced the release of Riviera 2004.08 with a direct simulation kernel connection with SystemC, creating a highly efficient system-level co-simulation environment for next generation ...
Design-Reuse

Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)

Riviera-PRO 2008.02 supports many features of the VHDL standard draft (IEEE P1076-2007/D4.0), recently approved by Accellera. Constructs such as new data types, subprograms and operators, matching ...
Semiconductor Engineering

Sigasi: Cleaner VHDL And SystemVerilog

Hardware engineers always have looked at software tools and methodologies with a certain degree of envy. While the hardware side has embraced the discipline necessary to get products right prior to ...
Design-Reuse

Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC

SystemC has gained wide acceptance in the design of new digital IPs. However, there are numerous IPs already designed in VHDL. With the advances in SystemC ecosystem, like IEEE standardization, TLM-2 ...