The 1T-SRAM-R macro is an enhanced single-transistor SRAM cell introduced early this year by MoSys, which shrunk the size of the memory circuit while adding ECC to the design for increased ...

Using the layout for the 450 nm technology node, our 2-tier 3D SRAM design achieves better integration density than the planar 350 nm node. Furthermore, we project up to 70% reduction in cell area for ...

A new technical paper titled “A New Ultralow-Voltage Retention SRAM Cell Enhancing Noise Immunity” was published by ...

Even as researchers investigate alternatives, silicon scaling is alive and kicking. IBM Corp. researchers will go to this week's IEDM with a presentation detailing an SRAM cell that meets the ...

Table 1: Cell summary Simulated results showing the dependence of bitline power is given in fig6. Power dissipation of 232 µW in full swing write is reduced to 60mW when DBL is lowered to of 400 mV.

The single transistor bit cell used in 1T-SRAM technology results in the technology achieving much higher density than traditional four or six transistor SRAMs while using the same standard logic ...

The Crolles2 Alliance has described at the VLSI Symposium in Kyoto, Japan, the creation, under production conditions, of six-transistor SRAM-bit cells with an area less than 0 ...