This adds more latency. Again the next instruction, which requires a memory block at address 32’h100, triggers cache line eviction and memory block fetching. This program results in poor performance ...

Direct mapped means that every memory location maps to just one cache location. In the diagram, there are 4 cache slots.This means that Cache index 0 might hold memory index 0,4,8 and so on.

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds ...