Munich, Germany — Atrenta Inc. has introduced its SpyGlass-DFT DSM design-for-test solution for deep submicron (DSM) circuits, supporting at-speed timing closure analysis, RTL testability improvement ...

The tool also provides a full timing-analysis environment for use during the design phase. Diagrams can be of analog or digital signals, with full support for advanced documentation constructs.

Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The ...

The basic methodologies for creating at-speed test patterns are covered in numerous sources.2 While creating at-speed test patterns, it is important to account for timing exceptions and ...