The coherence manager sends interventions to all cores where core 1 responds with a hit – ‘Modified.’ The coherence manager now initiates a write-back of the modified line, and moves line data ...

The basic cache coherence protocol is as follows: • The source node issues a read request (Fig. 1a). • The home node serializes (orders) and forwards requests (Fig. 1b).

By bringing the notion of cache coherence between the CPU and accelerator, CCIX bypasses much of the overhead. Data structures can be created in memory, and a pointer to it sent to the accelerator.